The invention relates to computing and can be used in arithmetic devices. A device for dividing binary numbers is known, which contains a divider register, an adder, a private register, a character analysis block, code transmission blocks, two AND elements, two OR elements, a corrective unit generating unit, connected in such a way that, depending on the comparison result of the divisor characters and the adder, the divider is transferred from the adder by a forward or reverse code through the code transmission blocks and a queued private digit is generated. The closest to the proposed is a device for dividing the numbers without restoring the remainder, containing the dividend register, the divider register, the private register, the c-matmator, the direct code to the additional code converter, the character analysis block, the private correction block, the AND elements, and OR elements connected According to the fact that, depending on the result of the analysis of the characters of the dividend and the divisor, the divider is transferred to the adder by a direct or reverse code through the code converter and the next private digit is generated. known devices, additional equipment costs for the implementation of AND elements and OR elements. The purpose of the invention is to simplify the device. The goal is achieved by the fact that the device for dividing numbers without restoring the remainder contains a divider register, the output of which is connected to the first input of the direct code to auxiliary converter, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the register of the dividend, block correction private, the first input of which is connected to the output of the high bit of the register of the dividend, and the second input is connected to the output of the high bit of the register of the divider and to the first input of the character analysis block D of which is connected to the low-order input of the private register, the output of the private correction block is connected to the output of the device and to the second input of the direct code to additional converter, the third input of which is connected to the low bit output of the private register, and the output of each digit of the adder is connected to the input of the corresponding times of the p d-a register of the dividend is shifted to the left by one bit, and the output of the high bit of the adder is connected to the second input of the character analysis block. The drawing shows a diagram of the proposed device. The device contains a register 1 divider, a converter 2 direct code into an additional, adder 3, register 4 divisible, block 5 analysis of characters, block b correction private, register 7 private, output 8 devices. The output of register 1 of the divider is connected to the first input of the converter 2 of the direct code to the additional one, the output of which is connected to the first input of the adder 3, the second input of the sum of the torus 2 is connected to the output of the register 4 of the dividend, the input of which is connected to the output of the adder 3 with a left shift bit. The output of the higher order of the register divider is connected to the first input of the character analysis block 5 and to the second input of the private correction block b. The output of the higher bit of sum 3 is connected to the second input of block 5 of character analysis, and the output of the high bit of register 4 divisible to the first input of block b is a private correction. The output of the character analysis block 5 is connected to the input of a dimmed register bit 7 of the private, the output of which is connected to the third input of the converter 2 of the direct code to the additional one, and the output of the block b of the correction of the private code with the second input of the converter 2 codes and with the output 8 devices. The device for dividing numbers without restoring the remainder works as follows. Before starting the calculation, the dividend is recorded in the register 4 of the dividend, the divisor is in the register 1 of the divider, the state of the private register 7 is indifferent, the private correction block B records in the trigger, which is in its composition, the value of the result of comparing the characters of the dividend and the divisor. If the signs of the operands in the initial state are equal, then in the first cycle of calculation the subtraction of the bodies from the dividend occurs, if the signs are not equal, the addition of the divisor and divimogue occurs in the first cycle of calculation. on adder 3. To do this, in the first cycle of the calculation by the manager, the operation of the direct code to additional converter is performed by the output of the private correction block b. Thus, the inputs of the adder 3, the first cycle of the calculation, receive the dividend in the forward code, and the divisor in the forward or additional code. At the end of the first cycle of calculation, by analyzing the divider character and the resulting amount, the character analysis unit 5 generates the value of the first private digit, which is the private sign, which is written to the low-order bit of the private 7 register simultaneously with a left shift by one bit. the resulting sum is equal to: then a one is written to the lower-order bit of the private register; if the characters are not equal, zero is written. At the same time, at the moment of recording the next digit of the quotient, the sum received on the adder 3 is written into the register 4 of the dividend with a left shift by one bit, while the lower bit of the register 4 of the dividend is written zero. In the second cycle, the value of the leading to the left sum from the register 4 of the dividend is fed to the input of the adder 3 in the forward code. The control of the operation of the direct code to the additional converter is no longer carried out by the output of the private correction unit 6, but by the low-order output of the private register 7, the value of which is the result of the analysis of the divisor characters and is non-mobile. sums of the previous calculation cycle. If the value of the quotient obtained in the previous cycle is one, then the divisor is fed to the adder. 3 in the additional code, if the quotient number is zero, then the divisor 3 is input to the input of the adder in the forward code. Receiving the next private digit is similar to the first cycle. Thus, starting with the second cycle in each cycle, transfer to. adder 3 divider controls the value of the -digit digit obtained in the previous cycle. Example. The divisible A 0,011, the divider B 0,111, the additional code of the divisor 1,001. e-ign A 0, B O, therefore, in the first cycle on the adder, the divisor B (A + J BlAon) I is subtracted from the dividend A. Since the recording of the next digit of the quotient in the register of the quotient 7 occurs at the moment of the shift to the left, the result of the division accumulates on this register. The number of cycles required is determined by the width of the operands. It should be noted that when dividing numbers, the device’s overflow grid is possibly overflowing ./ In these cases, the true result of the division operation is a number greater than / unit, or generally, a result of which is su- /
exists. Since devices operating with fixed-point numbers cannot represent numbers equal to 1 or 1, when dividing such numbers, the result obtained will be incorrect. Therefore, in order to generate a sign indicating an overflow in the discharge of the device’s grid, the output
sign
001